This invention relates generally to track and hold circuits and more specifically to a track and hold circuit having increased speed of operation.
As is known in the art, a track and hold circuit (sometimes also referred to as a sample and hold circuit), operates in either: a track mode, during which the level of an output voltage produced by the circuit tracks (i.e. is equal to) the level of an input voltage fed to the circuit; or, a subsequent hold mode, during which the output voltage is held constant at the last level tracked during the track mode. More particularly, the output voltage of the track and hold circuit varies in accordance with the voltage produced at a capacitor, such capacitor being coupled to the junction between a first current source and the collector electrode of a first one of a matched pair of transistors. The pair of transistors have interconnected emitter electrodes coupled to a second, constant current source providing a current of twice the level of the first current source. The control electrode of the first transistor is fed by the output voltage of the circuit and the control electrode of the second transistor is fed by the input voltage to the circuit.
With this arrangement, during the track mode, the capacitor is charged or discharged selectively in response to the difference between the levels of the output voltage and the input voltage. For example, when the input voltage level and output voltage level are equal, the second current source current is supplied equally through both of the pair of transistors. However, when the input voltage level is greater than that of the output voltage, the current from the second current source flows substantially through the second transistor. Excess current from the first current source is then available to charge the capacitor, thereby increasing the voltage produced at such capacitor and concomitantly increasing the output voltage until it is equal to the input voltage. On the other hand, when the input voltage level is less than that of the output voltage, less than one-half of the current for the second current source flows through the second transistor so the capacitor is discharged to supply current to the second current source. Such discharging of the capacitor causes a decrease in the level of the voltage produced at such capacitor, thereby decreasing the output voltage. When the hold mode is selected, the current sources are shut off so that no current is available for either charging or discharging the capacitor. In this way, the voltage produced at the capacitor, and concomitantly, the output voltage of the circuit, is held constant. In other words, in the hold mode, the output voltage level is equal to the last voltage level tracked during the track mode.
As is also known in the art, the flow of current through the transistors comprising the current sources does not cease instantaneously once the transistor is biased to its cutoff point. Thus, some current will be available to charge or discharge the capacitor even after hold mode operation has been selected, thereby slowing the transition from track mode to hold mode operation. Additionally, the current source transistors have junction capacitance which stores charge during the track mode. Such stored charge further slows the transition between the track and hold modes of operation. More specifically, the effect of the time constant associated with stopping the flow of current through the transistors and the junction capacitance stored charge is that the output voltage of the circuit may not be held constant upon selection of hold mode until after further charging or discharging of the capacitor, thereby introducing error into the operation of the circuit. In other words, the output voltage level held during the hold mode may not be equal to the last voltage level tracked during the track mode. This problem is aggravated in circuits in which the value of the capacitor is small, as small amounts of current (i.e. the stored charge) will change the voltage produced at such a capacitor.
One way known in the art for reducing the effect of residual charge stored in the current source transistor junction capacitance during the track mode is to minimize the voltage swing across the junctions of such transistors. However, while this technique may reduce the effect of stored charge on the track to hold mode transition, it does not eliminate the problem. Moreover, this technique does not address the problem associated with the time constant of biasing the current source transistors to their cutoff points. Thus, this solution may not be satisfactory, particularly in high speed circuits where the transition time between track and hold mode is critical.